Self-aligned GaAs FETs are widely used in high speed integrated circuits to minimize the gate-source and gate-drain parasitic resistances. Most self-aligned processes use a refractory gate metal (i.e. TiW) as a mask for self-aligned implantation of n+ source and drain ohmic regions. Refractory metals are used for their high temperature electrical, metallurgical stability during the post implant high temperature annealing of about 800.degree.-850.degree. C. This self-aligned n+ source and drain implant reduces the parasitic source and drain resistances, however in order to substantially reduce these parasitic resistances it is necessary to reduce the distance between source and drain ohmic contacts by developing a manufacturable process that allows for self-aligned deposition of source and drain metal contacts.
It is also important to be table to control the distance between gate metal and n+ source and drain implant regions, since they play an important role in both speed (through gate-source capacitance Cgs) and power (breakdown voltage VBgd) performance of a FET. A prior art patent, U.S. Pat. No. 4,782,032, issued to Geissberger et al on Nov. 1, 1988, addresses the control of n+ source and drain implants to the gate metal by using a "mushroom" or "T-shaped" gate process. This process requires the deposition of another layer either a dielectric or metal on top of the refractory metal and acts as the mask for subsequent etching and undercutting (in a controllable fashion) of the underlying refractory gate. The etching process is done either by wet chemical etch or dry etching. The sacrificial top layer is then removed prior to high temperature annealing of the n+ source and drain implants due to lack of high temperature stability of the top layer. Removing the top layer eliminates the choice of fabricating the ohmic metal contacts in a self-aligned manner with respect to the gate metal.
In another prior art patent, U.S. Pat. No. 4,712,219, issued to McLevige on Dec. 15, 1987, a high temperature stable material using a doped silicon layer is suggested that requires a complicated process of selectively etching and doping of a silicon layer, which is not a manufacturable process. There is no prior art that combines the "mushroom" or "T-shaped" gate process using a stable top layer for both self-align n+ source and drain implant, and ohmic contacts that is easily manufacturable.
It would be desirable, therefore, to devise a method of fabricating self-aligned FETs which is easily manufacturable.
It is a purpose of the present invention to provide a method of fabricating self-aligned FETs with both n+ implants and ohmic metals formed in a self-aligned fashion with respect to the gate which is easily manufacturable.
It is a further purpose of the present invention to provide a method of fabricating self-aligned FETs with controllable distances between gate metal and n+ source and drain implants.
It is a still further purpose of the present invention to provide a method of fabricating self-aligned FETs which eliminates any critical alignment of source and drain ohmic contacts.
It is a still further purpose of the present invention to provide a method of fabricating self-aligned FETs with improved speed performance for use in digital circuitry.
It is a still further purpose of the present invention to provide a method of fabricating self-aligned FETs which eliminates any critical processing steps for reducing gate resistance.